Computer memories are arranged into a plurality of addressable locations with each location utilized to store data. In order to access a location to read or write data at the location, an address corresponding to the location must be generated and input to the memory. As should be understood, a memory address must comprise a number of bits that is sufficient to uniquely identify each location of the memory. For example a 64 Kbyte RAM requires a 16 bit address to uniquely identify each memory location. As the memory capacity of modern computer systems expands, the number of bits required for the addresses used to access data has increased, as well. For instance, modern backplane bus based computer systems typically define an address space that encompasses all of the memory locations provided by all of the components coupled to the backplane bus. In this manner, each processor of the system can generate addresses for direct access to all of the memory locations available in the system.
However, when each processor of the system has a 64 Kbyte RAM local memory, a 16 bit address is sufficient for access to the locations of the local memory, as discussed above. Thus, each processor may include 16 line internal address busses, yet must generate a 32 bit address for access to non-local memory locations. In order to accommodate the disparity between local address bus size and the address size of a backplane bus address space, end-to-end registers are utilized to select an address within the 32 bit bus address space.
For example, two 16 bit registers arranged end-to-end can be used to transfer a 32 bit address from the 16 bit internal address bus to the 32 address lines of the backplane bus. The processor generates the first 16 high order bits of a 32 bit address and stores these bits in a first or high register. Thereafter, the processor generates the second 16 low order bits and stores these bits in a second or low register. The end-to-end arrangement of the two registers enables all 32 of the bits stored therein to be simultaneously transferred to the 32 address lines of the bus. However, as should be understood, the processor must generate two address segments and perform two register writes to transfer a 32 bit address to the backplane bus.
In another example, each processor of the system may be utilizing a 12 bit local memory address yet require a 16 bit bus address. In this instance, the high register can be arranged to store the 4 highest order bits of the 16 bit bus address with the remaining 12 low order bits being stored in a 12 bit low register. Thus, the 16 bit bus address is formed by concatenating the 4 bits of the high register with the 12 bits of the low register.
The end-to-end register arrangement can be used efficiently when a processor is accessing a number of memory locations within an area of the address space defined by the high order bits of the bus address. Under these circumstances, the processor need only generate and store the 16 low order bits for subsequent accesses to the area of the address space defined by the 16 high order bits in the 32 bit bus address example. The 16 high order bits are stored in the high register upon the first memory access operation to the area of the address space defined by the 16 high order bits and are reused so long as the processor continues to access memory locations within that particular area of the address space. The 16 low order bits for subsequent memory accesses define an offset within the particular area of the address space that locates the desired memory location. Similarly, in the 12 bit local address to 16 bit bus address example, the 4 bit register can be used to select a particular area of the address space with the 12 bit register being used to define an offset within the selected area during accesses to that particular area.
To summarize, a processor need only generate and store low order bits of an address when it is accessing locations within an area of the total memory that is defined by an n bit segment of the bus address if n equals the number of bits stored in the high register. This, however, imposes a limit to the efficiency provided by the end-to-end register arrangement.
The fixed size of the high register fixes the size of the area of the total memory that can be segmented for single register load operation. For example, when the processor is frequently accessing locations within an area of the address space that is defined by a number of bits that is less than the size of the high register, the processor must continue to generate the two segments of the bus address because the bits of the high register that are not used to define the particular area of the address space are required for the generation of the offset within that area.